01 / The cell · AI agents for semiconductor test

Move the program.Keep every decision.

Test programs carry years of engineering judgment. We’re building AI agents that port them from SmarTest 7 to SmarTest 8 (DC tests first), with every mapping traceable, every gap flagged for an engineer, and every port checked against its source.

See a port What runs today

Illustrative wafer · synthetic values

02 / Why it’s hard

Every chip is tested twice.WAFER SORT · FINAL TEST · $2–5M ATE PER CELL
The programs are written by hand.SUITES · LIMITS · BINNING · TRIBAL KNOWLEDGE
New floors are arriving faster than veterans can be trained.US CHIPS · INDIA ISM · EU CHIPS ACT

A floor: 18 testers, 3 senior engineers.

0 testers · 3 senior engineers Tester New floor capacity Senior test engineerSchematic · not to scale · hover to inspect

03 / The port

SmarTest 7 → 8. Intent first.

Proposed porting workflow · In development

01 ReadIntent-carrying values are found in the source: pins, forces, ranges, limits, test numbers, bins, logging.
02 ExtractEach value is lifted into a platform-independent record of test intent.
03 EmitThe target program is written from that record, with a thread back to every source line. Where the target’s shape differs, the change is declared.
04 FlagAnything without a confident mapping stops here, with a reason.
05 ReviewAn engineer resolves each flag. What cannot be resolved stays open, never defaulted.
06 CheckThe port is run against the source over pass, fail and flag scenarios: which tests execute, in what order, and which bin each part ends in.

Select any value in either program to see its mapping.

Source · SmarTest 7Illustrative syntax

 1suite    cont_io
 2  pins     
 3  force    
 4  measure  V  range 
 5  wait     
 6  limits    ..    test 
 7  on_fail  
 8  log      
 9suite    leak_vdd
10  pins     
11  force    
12  measure  I  range 
13  limits    ..    test 
14  on_fail  
15suite    idd_op
16  measure     test 30
17  limits   .. 12 mA   on_fail bin 5

Test intentPlatform-independent

0Pins

0Measurements

0Limits

0Flow

Target · SmarTest 8Illustrative syntax

 1suite ContIo_pos {
 2  group  {
 3    forceCurrent()
 4    measureVoltage(range: , settle: )
 5  }
 6  limit(, , )
 7  onFail()   log()
 8}
 9suite ContIo_neg extends ContIo_pos {
10  forceCurrent(-100 uA)   limit(t11, 0.40 V, 0.90 V)
11}
12suite LeakVdd {
13  group  { forceVoltage()  measureCurrent(range: ) }
14  limit(, , )
15  onFail()
16}
17// idd_op ·

Nothing silently assumed. Every difference made visible.

From running to proven

Every port ships with its report, and its proof.

Port report · cont_io, leak_vdd, idd_opSmarTest 7 → SmarTest 8 · DCExample · in development

#	Source	Intent	Target	Status
01	L2 · DUT_IO[0:7]	Signal group · 8 pins	L2 · DUT_IO[0:7]	Mapped · restructured
02	L3 · ±100 uA · both diodes	Force · current, two polarities	L3 · +100 uA	Declared mapping
03	L4 · 2 V	Measure · voltage range	L4 · 2 V	Mapped
04	L5 · settle_default	Settling time	L4 · 1.0 ms	Flagged → resolved
05	L6 · 0.40 V	Lower limit	L6 · 0.40 V	Mapped
06	L6 · 0.90 V	Upper limit	L6 · 0.90 V	Mapped
07	L6 · 10	Test numbers · 10 and 11	L6 · t10	Declared mapping
08	L7 · bin 3 stop	Fail action · soft bin 3, stop	L7 · bin(3), stop	Mapped
09	L8 · all	Logging	L7 · all	Mapped
10	L10 · VDD	Supply pin	L13 · VDD	Mapped · restructured
11	L11 · 3.30 V	Force · voltage	L13 · 3.30 V	Mapped
12	L12 · auto	Measure · current range	L13 · 10 uA	Flagged → resolved
13	L13 · -1.0 uA	Lower limit	L14 · -1.0 uA	Mapped
14	L13 · 1.0 uA	Upper limit	L14 · 1.0 uA	Mapped
15	L13 · 20	Test number	L14 · t20	Mapped
16	L14 · bin 4	Fail action · soft bin 4	L15 · bin(4), stop	Flagged → resolved
17	L16 · operating current	Measure · supply current under load	— · left open	Open

11 mapped · 2 declared · 4 flagged → 3 resolved by engineer · 1 open · 0 silently assumed

Flow check: 3 of 3 ported scenarios equivalent · 1 open, reported

04 / The proof · working today

Evidence before confidence.

The first real port is ahead of us. The two checks that will prove it already run.

Before any tester run · flow equivalenceRecorded experiment · runs today

A port that looks right can still bin wrong. We fail each test in turn and compare what the source does with what the port does: which tests run, in what order, and which bin the part ends in.

One generated program · 17 tests · fail each test in turnGenerator differs in 296 of 308 cases, same final bin in 265 · our port differs in 0 of 308

Select a row to read it. Each square is a test that ran; coral squares are tests the source never reached. Bins read soft / hard.

18 / 18

28 programs · 9,889 facts checked · 3 routes

Route	Silent errors	Flow-equivalent
Direct port	4	20 of 26
Through the intent record	0	23 of 26
Rules through the intent record	0	25 of 26

With the intent record in the loop, every remaining difference was flagged, not silent.

846 of 846 injected faults caught · 20 fault classes

2 defects found in the generator itself

Low and high limits exchanged in the limits table2 shipped programs, 14 of 14 comparable limits
Testing continues after a fail bin15 of 15 generated programs under documented SmarTest 8 binning

Generated programs. The SmarTest 7 to 8 test-method parameter mapping, where the real difficulty sits, is not exercised here.

Recorded experiment · 2026-09-30, re-scored 2026-10-08 · Origen-generated SmarTest 7/8 programs · not customer programs · SHA-256 5ee2b4ed…8625Download data ↗

On the tester · correlation

The correlation engine, working today.

After a port runs, the same devices’ datalogs are compared test by test. The engine that will do that already reads one STDF datalog blind and returns a diagnosis with an evidence chain.

DC parameter · same devices · both programsΔμ 24.0 mV · Δσ 55%

Source program (SmarTest 7) Target program (SmarTest 8)Illustrative · what the correlation report shows

Test 10 · Continuity · VRecorded ngspice simulation

200 / 200

Recorded ngspice LM358 simulation · not production tester data · STDF SHA-256 55658386…6705 · agent report SHA-256 26ae1bad…7691Download data ↗

Evidence chain · quoted from the agent’s report

Verdict · contactor wear · site 2 · onset device 62 · high confidence8 tool turns · 42.8 s · $0.09 · code 2122bb4

We raised contact resistance at one socket in a circuit simulation, then gave the agent only the STDF datalog, with no fault label. No device had failed its limits yet. The chain above is quoted from the agent’s report, not written for this page; select a line for the measurement behind it.

Acceptance sheetTargets for the first port · not results

Test list, numbers, units and limits identicalafter declared mappings · checked mechanically from both datalogs100%
Flow equivalence, source vs portbins, branches, sequence · checked on the program, before any tester run0 unflagged
Device pass/fail and soft-bin match, same unitsre-run of the same devices≥ 99%
Silent parameter dropsanything found in review that we did not flag0
Per-test mean and σinside an equivalence band agreed up frontIn band
Turnaround per program, once the pipeline existsnot weeksDays

05 / The arc

Give every test floor the judgment of a veteran test engineer, on demand.

01 ReadBuilt · proves every port
02 WriteNow · SmarTest 7 → 8 · DC tests
03 Optimize
04 Operate

Verified by physics

The verifier is measured data from the tester, not a model’s confidence in itself.

Vendor-neutral by design

STDF is the one datalog format every tester speaks. The proof does not depend on one vendor.

Proof before autonomy

Every port is checked against its source and correlated on the tester before anyone trusts it. The engineer reviews and decides.

END OF LOT · TP-DEMO-01 · ILLUSTRATIVE
PARTS 1200 · BIN1 1174 · BIN3 26 · FLAGGED 4 · RESOLVED 3 · OPEN 1 · PHASE LOCKED

06 / Contact

Working through a migration?

Pick the program. Don’t tell us what broke in your own port. We return the SmarTest 8 bundle, the port report and the flow check. You compare.

Tell us the platform pair and the test types.

team@truephase.ai